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公開日期標題作者
1-十二月-2017A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak PathHsieh, E. Ray; Kuo, Yen Chen; Cheng, Chih-Hung; Kuo, Jing Ling; Jiang, Meng-Ru; Lin, Jian-Li; Chen, Hung-Wen; Chung, Steve S.; Liu, Chuan-Hsi; Chen, Tse Pu; Huang, Shih An; Chen, Tai-Ju; Cheng, Osbert; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
201714奈米鰭式電晶體自熱效應的新穎溫度量測方法 及其對傳輸機制之影響江孟儒; 莊紹勳; Jiang, Meng-Ru; Chung, Steve S.; 電子研究所
20163D-TCAD Simulation Study of the Contact All Around T-FinFET Structure for 10nm Metal-Oxide-Semiconductor Field-Effect TransistorChou, Chen-Han; Hsu, Chung-Chun; Yeh, Wen-Kuan; Chung, Steve S.; Chien, Chao-Hsin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
20153D-TCAD Simulation Study of the Novel T-FinFET Structure for Sub-14nm Metal-Oxide-Semiconductor Field-Effect TransistorChou, Chen-Han; Hsu, Chung-Chun; Chung, Steve S.; Chien, Chao-Hsin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019The Advances of OTP Memory for Embedded Applications in HKMG Generation and BeyondChung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007The channel backscattering characteristics of sub-100nm CMOS devices with different channel/substrate orientationsTsai, Y. J.; Chung, Steve S.; Liu, P. W.; Tsai, C. H.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS TechnologyHsieh, E. R.; Hung, C. M.; Wang, T. Y.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Yew, T. R.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012CMOS製程相容U型多重讀寫氮化矽快閃式記憶體之物理機制與可靠性探討蔡政達; Tsai, Cheng-Ta; 莊紹勳; Chung, Steve S.; 電子研究所
2014A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance EffectsHung, C. M.; Li, K. C.; Hsieh, E. R.; Wang, C. T.; Kou, C. I.; Chang, Edward Y.; Chung, Steve S.; 材料科學與工程學系; 電子工程學系及電子研究所; Department of Materials Science and Engineering; Department of Electronics Engineering and Institute of Electronics
2015Demonstration of 3D Vertical RRAM with Ultra Low-leakage, High-selectivity and Self-compliance Memory CellsLuo, Qing; Xu, Xiaoxin; Liu, Hongtao; Lv, Hangbing; Gong, Tiancheng; Long, Shibing; Liu, Qi; Sun, Haitao; Banerjee, Writam; Li, Ling; Gao, Jianfeng; Lu, Nianduan; Chung, Steve S.; Li, Jing; Liu, Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019The Demonstration of Gate Dielectric -fuse 4kb OTP Memory Feasible for Embedded Applications in High -k Metal-gate CMOS Generations and BeyondHsieh, E. R.; Chang, C. W.; Chuang, C. C.; Chen, H. W.; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse BreakdownHsieh, E. R.; Huang, Z. H.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015Design of Complementary Tilt-gate TFETs with SiGe/Si and III-V Integrations Feasible for Ultra-low-power ApplicationsHsieh, E. R.; Lin, Y. S.; Zhao, Y. B.; Liu, C. H.; Chien, C. H.; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)Chung, Steve S.; Hsieh, E. R.; Liu, P. W.; Chiang, W. T.; Tsai, S. H.; Tsai, T. L.; Huang, R. M.; Tsai, C. H.; Teng, W. Y.; Li, C. I.; Kuo, T. F.; Wang, Y. R.; Yang, C. L.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G EraHsieh, E. R.; Wang, H. W.; Liu, C. H.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Embedded Resistive Switching Non-volatile Memory Technology for 28nm and Beyond High-k Metal-gate GenerationsChung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2018An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AIKuo, J. L.; Chen, H. W.; Hsieh, E. R.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2018An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFETHsieh, E. Ray; Jiang, Meng-Ru; Lin, Jian-Li; Chung, Steve S.; Chen, Tse Pu; Huang, Shih An; Chen, Tai-Ju; Cheng, Osbert; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS DevicesHsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2012Experimental Observation on the Random Dopant Fluctuation of Small Scale Trigate CMOS DevicesChung, Steve S.; 電子與資訊研究中心; Microelectronics and Information Systems Research Center
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