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國立陽明交通大學機構典藏
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公開日期
標題
作者
1-三月-2004
Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected balls
Lo, WY
;
Ker, MD
;
電機學院
;
College of Electrical and Computer Engineering
1-一月-2003
Active device under bond pad to save I/O layout for high-pin-count SOC
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
15-一月-2004
Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) process
Ker, MD
;
Tseng, TK
;
電機學院
;
College of Electrical and Computer Engineering
1-九月-2003
Analysis and prevention on NC-ball induced ESD damages in a 683-pin BGA packaged chipset IC
Lo, WY
;
Ker, MD
;
電機學院
;
College of Electrical and Computer Engineering
1-八月-2003
Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process
Chen, TY
;
Ker, MD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
1-八月-2003
Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product
Lin, IC
;
Huang, CY
;
Chao, CJ
;
Ker, MD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2001
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
Ker, MD
;
Jiang, HC
;
Peng, JJ
;
Shieh, TL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
1-九月-1996
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
Ker, MD
;
Wu, CY
;
Cheng, T
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
1-九月-1996
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
Ker, MD
;
Wu, CY
;
Cheng, T
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
1-三月-2000
Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
Ker, MD
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2004
Characterization on ESD devices with test structures in silicon germanium RF BiCMOS process
Ker, MD
;
Wu, WL
;
Chang, CY
;
電機學院
;
College of Electrical and Computer Engineering
1-六月-2003
CMOS chip as luminescent sensor for biochemical reactions
Lu, U
;
Hu, BCP
;
Shih, YC
;
Yang, YS
;
Wu, CY
;
Yuan, CJ
;
Ker, MD
;
Wu, TK
;
Li, YK
;
Hsieh, YZ
;
Hsu, WY
;
Lin, CT
;
機械工程學系
;
生物科技學系
;
應用化學系
;
電子工程學系及電子研究所
;
Department of Mechanical Engineering
;
Department of Biological Science and Technology
;
Department of Applied Chemistry
;
Department of Electronics Engineering and Institute of Electronics
2001
Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS process
Ker, MD
;
Lo, WY
;
Chen, TY
;
Tang, H
;
Chen, SS
;
Wang, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2002
Complementary substrate-triggered SCR devices for on-chip ESD protection circuits
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
1-四月-1996
Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI
Ker, MD
;
Wu, CY
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2004
Correlation between transmission-line-pulsing I-V curve and human-body-model ESD level on low temperature poly-Si TFT devices
Ker, MD
;
Hou, CL
;
Chang, CY
;
Chu, FT
;
電機學院
;
College of Electrical and Computer Engineering
1-二月-2005
Decreasing-size distributed ESD protection scheme for broad-band RF circuits
Ker, MD
;
Kuo, BJ
;
電機學院
;
College of Electrical and Computer Engineering
1-九月-2002
Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applications
Ker, MD
;
Chen, TY
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2000
Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications
Ker, MD
;
Chen, TY
;
Wu, CY
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2003
Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit
Ker, MD
;
Tsai, CS
;
電機學院
;
College of Electrical and Computer Engineering