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公開日期標題作者
1-三月-2004Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected ballsLo, WY; Ker, MD; 電機學院; College of Electrical and Computer Engineering
1-一月-2003Active device under bond pad to save I/O layout for high-pin-count SOCKer, MD; Peng, JJ; Jiang, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
15-一月-2004Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) processKer, MD; Tseng, TK; 電機學院; College of Electrical and Computer Engineering
1-九月-2003Analysis and prevention on NC-ball induced ESD damages in a 683-pin BGA packaged chipset ICLo, WY; Ker, MD; 電機學院; College of Electrical and Computer Engineering
1-八月-2003Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS processChen, TY; Ker, MD; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2003Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC productLin, IC; Huang, CY; Chao, CJ; Ker, MD; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC'sKer, MD; Jiang, HC; Peng, JJ; Shieh, TL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1996Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASICKer, MD; Wu, CY; Cheng, T; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1996Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASICKer, MD; Wu, CY; Cheng, T; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2000Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup dangerKer, MD; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004Characterization on ESD devices with test structures in silicon germanium RF BiCMOS processKer, MD; Wu, WL; Chang, CY; 電機學院; College of Electrical and Computer Engineering
1-六月-2003CMOS chip as luminescent sensor for biochemical reactionsLu, U; Hu, BCP; Shih, YC; Yang, YS; Wu, CY; Yuan, CJ; Ker, MD; Wu, TK; Li, YK; Hsieh, YZ; Hsu, WY; Lin, CT; 機械工程學系; 生物科技學系; 應用化學系; 電子工程學系及電子研究所; Department of Mechanical Engineering; Department of Biological Science and Technology; Department of Applied Chemistry; Department of Electronics Engineering and Institute of Electronics
2001Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS processKer, MD; Lo, WY; Chen, TY; Tang, H; Chen, SS; Wang, MC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002Complementary substrate-triggered SCR devices for on-chip ESD protection circuitsKer, MD; Hsu, KC; 電機學院; College of Electrical and Computer Engineering
1-四月-1996Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSIKer, MD; Wu, CY; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004Correlation between transmission-line-pulsing I-V curve and human-body-model ESD level on low temperature poly-Si TFT devicesKer, MD; Hou, CL; Chang, CY; Chu, FT; 電機學院; College of Electrical and Computer Engineering
1-二月-2005Decreasing-size distributed ESD protection scheme for broad-band RF circuitsKer, MD; Kuo, BJ; 電機學院; College of Electrical and Computer Engineering
1-九月-2002Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applicationsKer, MD; Chen, TY; Wu, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applicationsKer, MD; Chen, TY; Wu, CY; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuitKer, MD; Tsai, CS; 電機學院; College of Electrical and Computer Engineering
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