高速IC電源導線佈線和電容設計方法對板級電磁干擾影響探討

Abstract

本篇論文利用模擬電路板的電源導線電流迴路,將其電感減少,並且利用去耦合電容縮短電流迴路,找到有效抑制電磁干擾(EMI)的設計方法 . 在這整個迴路中有兩個參數為可變. 一是電流迴路大小, 二是印刷線路板電源導線粗細造成高頻時電感值大小. 進而產生同步切換雜訊(SSN),引發電磁干擾(EMI).

最後利用同步切換雜訊(SSN),將其時域轉換成頻域分析,得知遠場電磁干擾(EMI)之大小,有效降低電磁干擾除錯時間和快速找到雜訊來源.

In this thesis, we use demo board to simulate non-ideal return current paths. There are two key variables in a loop path. One is return current path, the other is the inductance in PCB power trace which voltage fluctuation is induced at high frequency, produces simultaneous switching noise and causes EMI issue. Finally, FFT is used to transfer simultaneous switching noise from time domain to frequency time to inspect far-field EMI spectrum, that is effective to reduce the debug schedule and find the root cause of EMI issue exactly.