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公開日期標題作者
七月-2016A Compact Subthreshold Model for Short-Channel Monolayer Transition Metal Dichalcogenide Field-Effect TransistorsYou, Wei-Xiang; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-2019Depolarization Field in Ferroelectric Nonvolatile Memory Considering Minor Loop OperationYou, Wei-Xiang; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2017Design Space Exploration Considering Back-Gate Biasing Effects for 2D Negative-Capacitance Field-Effect TransistorsYou, Wei-Xiang; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Design Space Exploration Considering Back-Gate Biasing Effects for Negative-Capacitance Transition-Metal-Dichalcogenide (TMD) Field-Effect TransistorsYou, Wei-Xiang; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2018Device Structural Effects on Negative-Capacitance FETsSu, Pin; You, Wei-Xiang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETsSu, Pin; You, Wei-Xiang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling ApproachSu, Pin; You, Wei-Xiang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Evaluation of 2D Negative-Capacitance FETs for Low-Voltage SRAM ApplicationsTseng, Kuei-Yang; You, Wei-Xiang; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2019Evaluation of NC-FinFET Based Subsystem-Level Logic CircuitsYou, Wei-Xiang; Su, Pin; Hu, Chenming; 電子工程學系及電子研究所; 國際半導體學院; Department of Electronics Engineering and Institute of Electronics; International College of Semiconductor Technology
1-一月-2018Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE SimulationYou, Wei-Xiang; Su, Pin; Hu, Chenming; 電子工程學系及電子研究所; 國際半導體學院; Department of Electronics Engineering and Institute of Electronics; International College of Semiconductor Technology
1-十月-2018Intrinsic Difference Between 2-D Negative-Capacitance FETs With Semiconductor-on-Insulator and Double-Gate StructuresYou, Wei-Xiang; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETsLee, Ho-Pei; Yu, Chien-Lin; You, Wei-Xiang; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Investigation of Short-Channel Effects in 2D Negative-Capacitance Field-Effect TransistorsYou, Wei-Xiang; Tsai, Chih-Peng; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2020A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FETYou, Wei-Xiang; Su, Pin; Hu, Chenming; 電子工程學系及電子研究所; 國際半導體學院; Department of Electronics Engineering and Institute of Electronics; International College of Semiconductor Technology
1-四月-2018Short-Channel Effects in 2D Negative-Capacitance Field-Effect TransistorsYou, Wei-Xiang; Tsai, Chih-Peng; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 15 筆資料，總共 15 筆