奈米尺寸之製程應變矽互補式金氧半場效電晶體之載子傳輸與負偏壓溫度不穩定之研究

Abstract

本論文中，我們主要探討製程引致單軸應力對互補式金氧半場效電晶體(CMOS)之載子傳輸(carrier transport)與負偏壓溫度不穩定(NBTI)的影響。載子傳輸方面，我們先以通道背向散射(channel backscattering)觀點來檢驗通道應力對高橫向電場下載子傳輸的影響。藉由背向散射參數與溫度的指數關係，我們可得一簡單的數學表示式以萃取通道背向散射係數(channel backscattering ratio)與相關參數，討論這些參數的變化對汲極電流的作用，並且分析何種機制造成應力引致背向散射參數的變化。我們亦探討通道應力對低橫向電場載子傳輸的作用。接著，我們提出一模型以關連低電場的載子傳輸與高電場下通道背向散射行為。依據此模型，我們首先提出一萃取源汲極寄生電阻的方法，可適用於奈米尺寸的製程應變矽CMOS，而無需處理通道遷移率與通道長度無關等等備受爭議的假設，以不同製程技術的CMOS來檢驗此模型並萃取其源汲極寄生電阻。最後，我們探討通道應力對負偏壓溫度不穩定(NBTI)的作用。

第二至第五章為載子傳輸的部分。第二章首先介紹通道背向散射理論及其電流電壓模型，接著比較幾種萃取通道背向散射率的方式。於本論文裡，我們利用背向散射參數與溫度的指數特性，推導出萃取背向散射率的數學式子，且考慮載子退化與寄生電阻對背向散射率的影響。第三章，使用製程應變矽(PSS) CMOS，從通道背向散射觀點來評估通道應力對高電場載子傳輸的影響。我們發現通道應力會改變CMOS其背向散射率，且隨著通道應力增加，背向散射率變化的幅度愈大，其中背向散射率的增加與降低與應力極性相關：具伸張應力的nMOSFETs會降低背向散射率；然而具壓縮應力的pMOSFETs會惡化背向散射率。這些變化對電流的作用，與造成此現象的機制亦涵蓋於第三章內。

第四章裡，我們提出一模型，此模型以源汲極寄生電阻、通道電阻、彈道傳輸率與寄生電阻的變化量等四個參數將製程引致的低電場通道遷移率增益、線性區與飽和區汲極電流增益關聯起來。此模型揭露出線性區、飽和區的汲極電流增益可表示為遷移率增益的線性函數，其截距大小與寄生電阻的變化量、源汲極電阻對通道電阻的比率有關。其中源汲極電阻對通道電阻的比率、彈道傳輸率分別決定著製程引致的遷移率增益對線性區、飽和區汲極電流增益的轉換效率。依據此模型，我們也發展出一適用於奈米尺寸製程應變矽CMOS其計算源汲極寄生電阻的方法。第五章裡，以不同製程技術的奈米通道尺寸應變矽CMOS來探討汲極電流增益、遷移率增益的關係，並且萃取其寄生電阻，分析比較不同製程技術對其影響。我們觀察到對任一製程技術而言，源汲極寄生電阻會逐漸地削減應變通道其提升電流的益處。我們也發現應變矽nMOSFETs與pMOSFETs其汲極電流增益與遷移率增益有一不同的比例關係。對nMOSFETs，其線性區與飽和區汲極電流增益大小相似，且電流的增益約只為通道遷移率增益的一半。然而對pMOSFETs，其線性區汲極電流增益比飽和區的來的大，與通道遷移率增益大小相似。造成此現象的機制亦探討之。

第六章則為通道應力對負偏壓溫度不穩定的作用探討。以三維應變工程來看，從通道寬度方向降低通道的壓縮應力，不僅有益於電流提升且改善元件其NBTI可靠度。此章節亦探討動態(dynamic)NBTI中退化回復的機制，與通道應力引致較大的NBTI退化之原因。最後於第七章裡，我們做一簡單摘要，並對此論文的延續工作與未來方向做一建議。

In this dissertation, we primarily investigate the impact of process-induced uniaxial strain of CMOSFETs on low-field carrier transport and high-field channel backscattering phenomenon. By utilizing the temperature power-dependence of drain current, we can deduce an analytic expression for extracting the channel backscattering ratio and related factors, and then analyze and discuss the mechanism responsible for strain-induced backscattering factor modulation. Here, we also propose a model for correlating the low-field carrier transport and high-field channel backscattering. According to this model, we develop a new methodology to extract the total source/drain (S/D) parasitic resistance for nanoscale strained MOSFETs. Then, we employ strained CMOSFETs by different technology nodes to examine our model and demonstrate the new extraction method. Finally, we study the effect of channel stress on negative bias temperature instability (NBTI) of pMOSFETs.

The channel backscattering theory, the current-voltage modeling, and the deduction of the analytic expression for evaluating the channel backscattering ratio are shown in Chapter 2. Then, we used process-strained Si (PSS) CMOSFETs to estimate its effect on carrier transport in terms of the backscattering factor modulation in Chapter 3. It is found that the channel stress results in the modulation of channel backscattering ratio, which becomes more evident with increasing channel stress. Moreover, the backscattering ratio modulation is dependent on stress polarity, i.e., tensile PSS nMOSFETs have decreased backscattering ratio whereas compressive PSS pMOSFETs exhibit increased backscattering ratio. The mechanism accounting for this observation is also discussed.

In Chapter 4, we proposed a model for correlating the strain-induced low-field channel mobility gain, linear drain current gain, and saturation drain current gain in terms of the S/D resistance, the channel resistance, the ballistic efficiency, and the reduction of S/D resistance. It is demonstrated for the first time that the linear and saturation drain current gains can be modeled as linear functions of channel mobility gain with the intercept of S/D resistance reduction, where the S/D-to-channel resistance ratio and the ballistic efficiency determine the translating efficiency of channel mobility gain to the linear and saturation drain current gains, respectively. Based on this model, we also developed a new methodology for extracting the total S/D parasitic resistance of nanoscale strained MOSFETs.

In Chapter 5, we employed state-of-the-art strained CMOSFETs by different technology nodes to examine the correlation between the channel mobility gain and drain current gain. We found that the S/D parasitic resistance gradually diminishes the benefit of strain-enhanced drain current gain regardless of adopting technology nodes. In addition, for PSS nMOSFETs, the linear and saturation drain current gains are comparable, where both current gains are around half of channel mobility gain. However, for PSS pMOSFETs, the linear drain current gain is comparable to the channel mobility gain and larger than the saturation one. The reasons accounting for this phenomenon are discussed as well.

In Chapter 6, we studied the NBTI of PSS pMOSFETs with different channel stress levels. It is noted that decreasing the channel compressive stress along the channel width direction not only improves the drain current but also the device reliability of NBTI. Moreover, mechanisms for degradation recovery during dynamic NBTI stress and aggravated NBTI degradation for pMOSFETs with larger channel stress are also discussed.

Finally, in Chapter 7, we summarize key findings and suggest the future works of this study.