使用金屬閘極及高介電常數介電質在絕緣層上有鍺電晶體之研究

Abstract

為了不斷地改善金氧半電晶體特性，提高電晶體的驅動電流及較小的漏電流是需要地。雖然高介電絕緣層可以大大降低閘極漏電流，但是對於高品質特性電路而言卻也大大降低了元件的遷移率。為了解決這個問題，我們完全利用了矽鍺的特性發展出一種低溫絕緣層上有鍺電晶體，可以能達到低缺陷。因此，在沒有缺陷特性之下的高良率，電洞及電子的遷移率可以大大的改善，及沒有發生高介電絕緣層的結晶化、介面反應及等效氧化層的減少。除此之外，我們所發展之低溫絕緣層上有鍺電晶體的遷移率大約比一般矽元件大兩倍。 為了進一步發展絕緣層上有鍺電晶體的製程，我們使用此製程來降低在連接線上交流功率；我們也發展出結合自我對準的金屬閘極/高介電絕緣層/絕緣層上有鍺電晶體在一層複晶矽-六層金屬之0.18-um矽元件上；因為交流功率的問題是比直流功率所引起閘極漏電流更為嚴重。從使用電磁方法來直接計算交流功率，我們可以計算出交流功率的消耗及最大操作頻率，藉此可以結合附加的積體電路層數。這些令人振奮的結果，是由於絕緣層上有鍺電晶體的製程是低溫的製程符合了三度空間元件積體化所需要的低溫製程。而三度空間互補式金氧半電晶體也提供了尺寸微縮新的契機，因此解決了二度空間互補式金氧半電晶體量子理論的限制。除此之外，也降低了交流功率的消耗。由於絕緣層上有鍺電晶體元件高品質的特性和三度空間元件積體化的製程是符合現今超大型積體電路的製程，所以這個製程是對未來超大型積體電路有相當的貢獻。

To continuously improve the MOSFET performance, both higher drive current and smaller leakage current are required. Although the high-k MOSFETs can reduce the gate leakage current by orders of magnitude, the much degraded mobility is unacceptable for high performance circuits. To overcome this problem, we have developed a low temperature GOI process to fully utilize the merit of SiGe and achieve low dislocation simultaneously. Therefore, both hole and electron mobility can be largely improved in GOI with unique merits of dislocation free property for high yield, no high-k crystallization, nor interface reaction or EOT reduction. In addition, the mobilities of the low temperature GOI devices are ~2-times higher than universal mobility values. Extending the GOI process, we also integrated self-aligned metal gate/high-k/GOI on 1-Poly-6-Metal (1P6M) 0.18-um Si devices to reduce the AC power consumption in interconnects, which is the most severe issue beyond the DC power arising from the gate dielectric leakage current. From a direct calculation of the AC power consumption, using an Electro-Magnetic method, we show that both the AC power consumption and maximum operation frequency can be improved by integrating an additional IC layer. These promising results are due to the low temperature GOI device process, which is well-matched to the low thermal budget requirements of three-dimensional (3D) integration. The good 3D CMOS may also provide equivalent scaling extension after 2D CMOS approaches the quantum mechanics limit, in addition to the advantage of low AC power consumption. The high performance GOI devices and simple 3D integration process, compatible to current VLSI technology, should be useful for future VLSI.