具奈米尺度及新穎結構的高效能低溫複晶矽薄膜電晶體的製作與特性研究

Abstract

在此論文第一部分中，我們首先製作具有多重奈米線通道(multiple nanowire channels)與輕掺雜汲極(Lightly-Doped Drain)結構的短通道(閘極長度為0.5um)複晶矽薄膜電晶體(poly-Si TFTs)，並研究在具有不同通道寬度和數目下，元件的操作特性與其在直流及交流應力壓迫下的可靠度分析。由實驗結果發現，在同為閘極長度(gate length)為0.5 um下，具有十條奈米導線通道（每條寬度為67奈米）的複晶矽薄膜電晶體 (M10 TFT)，展現出較其他不同通道寬度和數目的複晶矽薄膜電晶體，較優越且較穩定的電特性。包括有較高的開關電流比(>109)，較陡峭的次臨界導通斜率(Subthreshold Swing)，極小的汲極導致能障下降 (Drain-Induced Barrier Lowing)，較佳的糾結效應(kink-effect)抑制能力，與較佳的製程穩定度(Stability)。此外在可靠度的研究中，M10 TFT展現極佳的抗應力(stress)的能力，其臨界電壓和次臨界導通斜率幾乎不隨應力壓迫時間而改變。總結原因首先是M10 TFT具有分立奈米線，使得閘極環跨於通道時，形成環繞式的三向閘極(tri-gate)，而具有最佳的閘極控制能力，進而可抑制複晶矽薄膜電晶體的短通道效應(short-channel effect)及不理想效應(non-ideal effect)。其次是，M10 TFT其分立奈米線通道結構，在其進行及較好的氨電漿鈍化保護時，較單一通道的複晶矽薄膜電晶體，具有較大的氨電漿鈍化保護面積，而達到較佳的氨電漿保護效果。另一方面，由一系列的實驗結果發現，閘極的控制能力是隨著通道寬度的縮減而增強，其原因為元件的閘極結構由單一閘極(single-gate)轉換為三向閘極(tri-gate)所致。此閘極控制能力佳、高效能、高可靠度，且不需額外製程的新穎結構之TFT，將可被廣泛的運用在主動式矩陣液晶顯示器(AMLCD) 以及三維立體之金氧半場效電晶體（3D MOSFET）積體電路元件上。 在此論文第二部分，我們首先提出一種新穎的4道光罩製程的元件圖案相依之金屬誘化側向結晶複晶矽薄膜電晶體(pattern-dependent metal-induced lateral crystallization polysilicon thin-film transistors: PDMILC poly-Si TFTs)。並研究一系列不同通道寬度及其通道數目之的尺寸效應及其氨電漿保護效應。在我們的實驗結果中顯示，電晶體的場效載子移動率(field effect mobility)，隨著通道寬度下降而提升，此乃由於在金屬誘化側向結晶過程中，複晶矽成長時，窄通道寬度局限下，而使得複晶矽的側向長度提升。進一步地，將此元件圖案相依金屬誘化側向結晶複晶矽薄膜電晶體，進行氨電漿處理，由實驗結果中顯示，經過氨電漿鈍化保護後之元件，擁有較高之場效載子移動率(提升約2倍)、較高之開關電流比（>106）、較為陡峭之次臨界斜率（230 mV/decade），此乃由於氨電漿中的氫原子將可有效的填補複晶矽邊界之懸浮鍵，及氮原子會堆積在二氧化矽/複晶矽表面形成介面保護。並且隨著通道數目的增加，由於受氨電漿保護的接觸面積也跟著增加。實驗結果顯示，在十條奈米線（每條寬度為67奈米）的通道元件將有優於其他結構的元件特性。 進一步地，我們探討利用多重閘極(multi-gate)配合多條奈米線(nanowire)通道之圖案相依金屬誘化側向結晶薄膜電晶體的結構。在實驗結果中顯示，多重閘極搭配十條奈米線通道可進一步的提升元件特性，如具有有更低的漏電流、更高的開關電流比、更低的臨界電壓、更為陡峭的次臨界斜率，並可同時抑制紐結效應(Kink effect)，以及具有較佳的可靠度。總結之，將元件圖案相依金屬誘化側向結晶薄膜電晶體製程中多加一道氨電漿處理，以及改變單一閘極為多重閘極結構，皆可大幅提升元件特性以及降低薄膜電晶體之不理想效應。此元件圖案相依金屬誘化側向結晶薄膜電晶體的製程技術，可與現今的互補式金屬氧化物半導體(CMOS)製程技術相結合，而且不必再添加額外的光罩。此高效能之元件圖案相依金屬誘化側向結晶薄膜電晶體將可應用在主動式矩陣液晶顯示器以及三維立體之金氧半場效電晶體（3D MOSFET）積體電路元件上。

In first part, we study the electrical characteristics of a series of polysilicon thin-film transistors (poly-Si TFTs) with different numbers of multiple channels of various widths, with lightly-doped drain (LDD) structures. Among all investigated TFTs, the nano-scale TFT with ten 67 nm-wide split channels (M10) has superior and more uniform electrical characteristics than other TFTs, such as a higher ON/OFF current ratio (>109), a steeper subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL) and a suppressed kink-effect. These results originate from the fact that the active channels of M10 TFT has best gate control due to its nano-wire channels were surrounded by tri-gate electrodes. Additionally, experimental results reveal that the electrical performance of proposed TFTs enhances with the number of channels from one to ten strips of multiple channels sequentially, yielding a profile from a single gate to tri-gate structure. Additionally, NH3-plasma passivation more efficiently affects M10 TFT than it does other TFTs. The M10 TFT has a split nano-wire structure, most of which is exposed to NH3 plasma passivation, further reducing the number of grain boundary defects. On the other hand, the ac and dc reliability of ten-nanowire poly-Si TFTs are investigated. In static and dynamic hot-carrier stress experiments, the ten-nanowire poly-Si TFTs reduces the degradation of Vth, SS, Ion, On/OFF ratio and DIBL, for all kind of frequency, rising time, falling time and temperature, compared to single-channel TFT. These high reliability results of multiple nanowire poly-Si TFTs can be also explained by its robust tri-gate control and its superior channel NH3 passivation on the poly-Si grain boundary. Devices that contain the proposed M10 TFT are highly promising for use in active-matrix liquid-crystal-display and 3-D CMOS technologies without any additional processing. In second part, the effects of channel width and NH3 plasma passivation on the electrical characteristics of a series of a novel 4-mask pattern-dependent metal-induced lateral crystallization (PDMILC) polysilicon thin-film transistors (poly-Si TFTs) were studied. The mobility and device performance of PDMILC TFTs improves as the each channel width decreasing. Furthermore, PDMILC TFTs with NH3 plasma passivation outperforms without such passivation, resulting from the effective hydrogen passivation of the grain-boundary dangling bonds, and the pile-up of nitrogen at the SiO2/poly-Si interface. In particular, the electrical characteristics of a nano-scale TFT with ten 67 nm-wide split channels (M10) are superior to those of other TFTs. The former include a higher field effect mobility of 84.63 cm2/Vs, a higher ON/OFF current ratio (>106), a steeper subthreshold slope (SS) of 230 mV/decade, an absence of drain-induced barrier lowering (DIBL). These findings originate from the fact that the active channels of the M10 TFT have exhibit most poly-Si grain enhanced to reduce the grain boundary defects and best NH3 plasma passivation due to its split nanowire structure. Both effects can reduce the number of defects at grain boundaries of poly-Si in active region for high performances. In addition, we have also studied the multi-gate combining the pattern-dependent nickel (Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels. Experimental results reveal that applying ten nanowire channels improves the performance of Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current and a lower threshold voltage (Vth) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multi-gate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low Vth, a steep subthreshold swing (SS) and kink-free output characteristics. The multi-gate with ten nanowire channels NI-MILC TFTs has few poly-Si grain boundary defects, a low lateral electrical field and a gate channel shortening effect, all of which are associated with such high-performance characteristics. The PDMILC TFTs process is compatible with CMOS technology, and involves no extra mask. Such high performance PDMILC TFTs are thus promising for use in future high-performance poly-Si TFT applications, especially in AMLCD and 3D MOSFET stacked circuits.