标题: | 具奈米尺度及新颖结构的高效能低温复晶矽薄膜电晶体的制作与特性研究 Fabrication and Characterization of Novel Structure with Nano-Scale Low-Temperature High-Performance Polysilicon Thin-film Transistors |
作者: | 吴永俊 Yung-Chun Wu 张俊彦 Chun-Yen Chang 电子研究所 |
关键字: | 复晶矽薄膜电晶体;奈米线;三向闸极;元件图案相依的金属诱化侧向结晶;多重闸极;主动式液晶显示器;Polysilicon thin-film transistors;Nanowire;Tri-gate;Pattern-depended metal induced lateral crystallization;Multi-gate;AMLCD |
公开日期: | 2005 |
摘要: | 在此论文第一部分中,我们首先制作具有多重奈米线通道(multiple nanowire channels)与轻掺杂汲极(Lightly-Doped Drain)结构的短通道(闸极长度为0.5um)复晶矽薄膜电晶体(poly-Si TFTs),并研究在具有不同通道宽度和数目下,元件的操作特性与其在直流及交流应力压迫下的可靠度分析。由实验结果发现,在同为闸极长度(gate length)为0.5 um下,具有十条奈米导线通道(每条宽度为67奈米)的复晶矽薄膜电晶体 (M10 TFT),展现出较其他不同通道宽度和数目的复晶矽薄膜电晶体,较优越且较稳定的电特性。包括有较高的开关电流比(>109),较陡峭的次临界导通斜率(Subthreshold Swing),极小的汲极导致能障下降 (Drain-Induced Barrier Lowing),较佳的纠结效应(kink-effect)抑制能力,与较佳的制程稳定度(Stability)。此外在可靠度的研究中,M10 TFT展现极佳的抗应力(stress)的能力,其临界电压和次临界导通斜率几乎不随应力压迫时间而改变。总结原因首先是M10 TFT具有分立奈米线,使得闸极环跨于通道时,形成环绕式的三向闸极(tri-gate),而具有最佳的闸极控制能力,进而可抑制复晶矽薄膜电晶体的短通道效应(short-channel effect)及不理想效应(non-ideal effect)。其次是,M10 TFT其分立奈米线通道结构,在其进行及较好的氨电浆钝化保护时,较单一通道的复晶矽薄膜电晶体,具有较大的氨电浆钝化保护面积,而达到较佳的氨电浆保护效果。另一方面,由一系列的实验结果发现,闸极的控制能力是随着通道宽度的缩减而增强,其原因为元件的闸极结构由单一闸极(single-gate)转换为三向闸极(tri-gate)所致。此闸极控制能力佳、高效能、高可靠度,且不需额外制程的新颖结构之TFT,将可被广泛的运用在主动式矩阵液晶显示器(AMLCD) 以及三维立体之金氧半场效电晶体(3D MOSFET)积体电路元件上。 在此论文第二部分,我们首先提出一种新颖的4道光罩制程的元件图案相依之金属诱化侧向结晶复晶矽薄膜电晶体(pattern-dependent metal-induced lateral crystallization polysilicon thin-film transistors: PDMILC poly-Si TFTs)。并研究一系列不同通道宽度及其通道数目之的尺寸效应及其氨电浆保护效应。在我们的实验结果中显示,电晶体的场效载子移动率(field effect mobility),随着通道宽度下降而提升,此乃由于在金属诱化侧向结晶过程中,复晶矽成长时,窄通道宽度局限下,而使得复晶矽的侧向长度提升。进一步地,将此元件图案相依金属诱化侧向结晶复晶矽薄膜电晶体,进行氨电浆处理,由实验结果中显示,经过氨电浆钝化保护后之元件,拥有较高之场效载子移动率(提升约2倍)、较高之开关电流比(>106)、较为陡峭之次临界斜率(230 mV/decade),此乃由于氨电浆中的氢原子将可有效的填补复晶矽边界之悬浮键,及氮原子会堆积在二氧化矽/复晶矽表面形成介面保护。并且随着通道数目的增加,由于受氨电浆保护的接触面积也跟着增加。实验结果显示,在十条奈米线(每条宽度为67奈米)的通道元件将有优于其他结构的元件特性。 进一步地,我们探讨利用多重闸极(multi-gate)配合多条奈米线(nanowire)通道之图案相依金属诱化侧向结晶薄膜电晶体的结构。在实验结果中显示,多重闸极搭配十条奈米线通道可进一步的提升元件特性,如具有有更低的漏电流、更高的开关电流比、更低的临界电压、更为陡峭的次临界斜率,并可同时抑制纽结效应(Kink effect),以及具有较佳的可靠度。总结之,将元件图案相依金属诱化侧向结晶薄膜电晶体制程中多加一道氨电浆处理,以及改变单一闸极为多重闸极结构,皆可大幅提升元件特性以及降低薄膜电晶体之不理想效应。此元件图案相依金属诱化侧向结晶薄膜电晶体的制程技术,可与现今的互补式金属氧化物半导体(CMOS)制程技术相结合,而且不必再添加额外的光罩。此高效能之元件图案相依金属诱化侧向结晶薄膜电晶体将可应用在主动式矩阵液晶显示器以及三维立体之金氧半场效电晶体(3D MOSFET)积体电路元件上。 In first part, we study the electrical characteristics of a series of polysilicon thin-film transistors (poly-Si TFTs) with different numbers of multiple channels of various widths, with lightly-doped drain (LDD) structures. Among all investigated TFTs, the nano-scale TFT with ten 67 nm-wide split channels (M10) has superior and more uniform electrical characteristics than other TFTs, such as a higher ON/OFF current ratio (>109), a steeper subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL) and a suppressed kink-effect. These results originate from the fact that the active channels of M10 TFT has best gate control due to its nano-wire channels were surrounded by tri-gate electrodes. Additionally, experimental results reveal that the electrical performance of proposed TFTs enhances with the number of channels from one to ten strips of multiple channels sequentially, yielding a profile from a single gate to tri-gate structure. Additionally, NH3-plasma passivation more efficiently affects M10 TFT than it does other TFTs. The M10 TFT has a split nano-wire structure, most of which is exposed to NH3 plasma passivation, further reducing the number of grain boundary defects. On the other hand, the ac and dc reliability of ten-nanowire poly-Si TFTs are investigated. In static and dynamic hot-carrier stress experiments, the ten-nanowire poly-Si TFTs reduces the degradation of Vth, SS, Ion, On/OFF ratio and DIBL, for all kind of frequency, rising time, falling time and temperature, compared to single-channel TFT. These high reliability results of multiple nanowire poly-Si TFTs can be also explained by its robust tri-gate control and its superior channel NH3 passivation on the poly-Si grain boundary. Devices that contain the proposed M10 TFT are highly promising for use in active-matrix liquid-crystal-display and 3-D CMOS technologies without any additional processing. In second part, the effects of channel width and NH3 plasma passivation on the electrical characteristics of a series of a novel 4-mask pattern-dependent metal-induced lateral crystallization (PDMILC) polysilicon thin-film transistors (poly-Si TFTs) were studied. The mobility and device performance of PDMILC TFTs improves as the each channel width decreasing. Furthermore, PDMILC TFTs with NH3 plasma passivation outperforms without such passivation, resulting from the effective hydrogen passivation of the grain-boundary dangling bonds, and the pile-up of nitrogen at the SiO2/poly-Si interface. In particular, the electrical characteristics of a nano-scale TFT with ten 67 nm-wide split channels (M10) are superior to those of other TFTs. The former include a higher field effect mobility of 84.63 cm2/Vs, a higher ON/OFF current ratio (>106), a steeper subthreshold slope (SS) of 230 mV/decade, an absence of drain-induced barrier lowering (DIBL). These findings originate from the fact that the active channels of the M10 TFT have exhibit most poly-Si grain enhanced to reduce the grain boundary defects and best NH3 plasma passivation due to its split nanowire structure. Both effects can reduce the number of defects at grain boundaries of poly-Si in active region for high performances. In addition, we have also studied the multi-gate combining the pattern-dependent nickel (Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels. Experimental results reveal that applying ten nanowire channels improves the performance of Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current and a lower threshold voltage (Vth) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multi-gate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low Vth, a steep subthreshold swing (SS) and kink-free output characteristics. The multi-gate with ten nanowire channels NI-MILC TFTs has few poly-Si grain boundary defects, a low lateral electrical field and a gate channel shortening effect, all of which are associated with such high-performance characteristics. The PDMILC TFTs process is compatible with CMOS technology, and involves no extra mask. Such high performance PDMILC TFTs are thus promising for use in future high-performance poly-Si TFT applications, especially in AMLCD and 3D MOSFET stacked circuits. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009111817 http://hdl.handle.net/11536/44423 |
显示于类别: | Thesis |
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